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HYS 64V8301GU SDRAM-Modules
3.3 V 8M x 64-Bit 1 Bank SDRAM Module 168-pin Unbuffered DIMM Modules
* 168 Pin unbuffered 8 Byte Dual-In-Line SDRAM Modules for PC main memory applications * PC100 and PC133 versions * One bank 8M x 64 organization * Optimized for byte-write non-parity applications * JEDEC standard Synchronous DRAMs (SDRAM) * Fully PC board layout compatible to INTEL's latest module specification * SDRAM Performance: -7.5 PC133 -8 PC100 100 MHz Unit * Programmed Latencies: Product Speed -7.5 -8 CL
tRCD
3 2
tRP
3 2
PC133 3 PC100 2
* Single 3.3 V ( 0.3 V) power supply * Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) * Auto Refresh (CBR) and Self Refresh * Decoupling capacitors mounted on substrate * All inputs and outputs are LVTTL compatible * Serial Presence Detect with E2PROM * Utilizes four 8M x 16 SDRAMs in TSOPII-54 packages with 4096 refresh cycles every 64 ms * 133.35 mm x 29.31 mm x 4.00 mm card size with gold contact pads
fCK Clock
Frequency (max.)
133
tAC Clock Access 5.4
Time
6
ns
The HYS 64V8301 is an industry standard 168-pin 8-byte Dual in-line Memory Module (DIMM) which is organized as 8M x 64 in an one bank high speed memory arrays designed with 128 Mbit Synchronous DRAMs for non-parity applications. The DIMMs use -7.5 speed sorted 4M x 16 SDRAM devices in TSOP54 packages to meet the PC133-333 requirements and -8 parts for the standard PC100 applications. Decoupling capacitors are mounted on the PC board. The PC board design is according to INTEL's module specification. The DIMMs have a serial presence detect, implemented with a serial E2PROM using the 2-pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user. All Infineon 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133.35 mm long footprint.,
Data Book
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HYS 64V8301GU SDRAM-Modules
Ordering Information Type HYS 64V8301GU-7.5-C HYS 64V8301GU-8-C Code Package Description Module
Height
PC133-333-520 L-DIM-168-32 133 MHz 4M x 64 1 bank SDRAM module PC100-222-620 L-DIM-168-32 100 MHz 4M x 64 1 bank SDRAM module
1.15" 1.15"
Note: All part numbers end with a place code (not shown), designating the die revision. Consult factory for current revision. Example: HYS64V4300GU-8-C, indicating Rev.C dies are used for SDRAM components.
Pin Definitions and Functions A0 - A11 Address Inputs (RA0 ~ RA11 / CA0 ~ CA7, CA10) Bank Select Data Input/Output Check Bits (x72 organization only) Row Address Strobe Column Address Strobe Read/Write Input CLK0 - CLK3 Clock Input
BA0, BA1 DQ0 - DQ63 CB0 - CB7 RAS CAS WE
DQMB0 - DQMB7 Data Mask CS0 - CS3 Chip Select Power (+ 3.3 V) Ground Clock for Presence Detect Serial Data Out for Pres. Detect No Connection
VDD VSS
SCL SDA N.C./DU
CKE0, CKE1 Clock Enable
Address Format Part Number 8M x 64 HYS 64V8301GU Rows Columns Bank Select 12 9 2 Refresh 4k Period 64 ms Interval 15.6 s
Data Book
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HYS 64V8301GU SDRAM-Modules
Pin Configuration PIN#
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
Symbol
VSS
DQ0 DQ1 DQ2 DQ3
PIN#
43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
Symbol
VSS
DU CS2 DQMB2 DQMB3 DU
PIN#
85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126
Symbol
VSS
DQ32 DQ33 DQ34 DQ35
PIN#
127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168
Symbol
VSS
CKE0 CS3 DQMB6 DQMB7 N.C.
VDD
DQ4 DQ5 DQ6 DQ7 DQ8
VDD
DQ36 DQ37 DQ38 DQ39 DQ40
VDD
N.C. N.C. N.C. N.C.
VDD
N.C. N.C. CB6 CB7
VSS
DQ9 DQ10 DQ11 DQ12 DQ13
VSS
DQ16 DQ17 DQ18 DQ19
VSS
DQ41 DQ42 DQ43 DQ44 DQ45
VSS
DQ48 DQ49 DQ50 DQ51
VDD
DQ20 N.C. DU CKE1
VDD
DQ52 N.C. DU N.C.
VDD
DQ14 DQ15 N.C. N.C.
VDD
DQ46 DQ47 N.C. N.C.
VSS
DQ21 DQ22 DQ23
VSS
DQ53 DQ54 DQ55
VSS
N.C. N.C.
VSS
N.C. N.C.
VDD
WE DQMB0 DQMB1 CS0 DU
VSS
DQ24 DQ25 DQ26 DQ27
VDD
CAS DQMB4 DQMB5 CS1 RAS
VSS
DQ56 DQ57 DQ58 DQ59
VDD
DQ28 DQ29 DQ30 DQ31
VDD
DQ60 DQ61 DQ62 DQ63
VSS
A0 A2 A4 A6 A8 A10 BA1
VSS
A1 A3 A5 A7 A9 BA0 A11
VSS
CLK2 N.C. WP SDA SCL
VSS
CLK3 N.C. SA0 SA1 SA2
VDD VDD
CLK0
VDD
CLK1 N.C.
VDD
VDD
Data Book
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HYS 64V8301GU SDRAM-Modules
Functional Block Diagrams
CS0 CS LDQM DQ0-DQ7 UDQM DQ8-DQ15 D0 CS2 CS LDQM DQ0-DQ7 UDQM DQ8-DQ15 D1 A0-A11, BA0, BA1 D0-D3, (D4) D0-D3, (D4) CS LDQM DQ0-DQ7 UDQM DQ8-DQ15 D3 E 2 PROM (256 word x 8 Bit) SA0 SA1 SA2 SCL SA0 SA1 SA2 SCL SDA WP 47 k CS LDQM DQ0-DQ7 UDQM DQ8-DQ15 D2
DQMB0 DQ0-DQ7 DQMB1 DQ8-DQ15
DQMB4 DQ32-DQ39 DQMB5 DQ40-DQ47
DQMB2 DQ16-DQ23 DQMB3 DQ24-DQ31
DQMB6 DQ48-DQ55 DQMB7 DQ56-DQ63
VCC C VSS
RAS, CAS, WE CKE0 CLK1, CLK3
D0-D3, (D4) D0-D3, (D4) D0-D3
Clock Wiring 4 M x 64
10 pF Notes:
CLK0 CLK1 CLK2 CLK3
2 SDRAM + 15 pF Termination 2 SDRAM + 15 pF Termination
1) All resistors are 10 2) DIMM may combine bytes 0 with 4, 1 with 5, 2 with 6 and 3 with 7 to obtain most advantagous board layout to obtain minimum DQ trance length
SPB04204
Block Diagram: 4M x 64 One Bank SDRAM DIMM Modules (HYS 64V4300GU)
Data Book
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HYS 64V8301GU SDRAM-Modules
DC Characteristics TA = 0 to 70 C; VSS = 0 V; VDD; VDDQ = 3.3 V 0.3 V Parameter Input High Voltage Input Low Voltage Output High Voltage (IOUT = - 4.0 mA) Output Low Voltage (IOUT = 4.0 mA) Input Leakage Current, any input (0 V < VIN < 3.6 V, all other inputs = 0 V) Output Leakage Current (DQ is disabled, 0 V < VOUT < VDD) Capacitance TA = 0 to 70 C; VDD = 3.3 V 0.3 V, f = 1 MHz Parameter Input Capacitance (A0 - A11, RAS, CAS, WE) Input Capacitance (CS0 , CS2) Input Capacitance (CLK0 - CLK3) Input Capacitance (CKE0) Input Capacitance (DQMB0 - DQMB7) Input /Output Capacitance (DQ0 - DQ63, CB0 - CB7) Input Capacitance (SCL, SA0-2) Input /Output Capacitance Symbol Limit Values max. 35 25 35 30 13 10 8 8 Unit pF pF pF pF pF pF pF pF Symbol min. Limit Values max. 2.0 - 0.5 2.4 - - 10 - 10 Unit V V V V A A
VIH VIL VOH VOL II(L) IO(L)
VDD + 0.3
0.8 - 0.4 10 10
CI1 CI2 CICL CI3 CI4 CIO CSC CSD
Data Book
5
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HYS 64V8301GU SDRAM-Modules
Operating Currents 1 TA = 0 to 70 C, VDD = 3.3 V 0.3 V (Recommended Operating Conditions unless otherwise noted) Parameter Operating current tRC = tRC(MIN.), tCK = tCK(MIN.) Outputs open, Burst Length = 4, CL=3 All banks operated in random access, all banks operated in ping-pong manner to maximize gapless data access Precharge standby current in Power Down Mode CS = VIH (MIN.), CKE VIL(MAX.) Precharge stand-by current in Non Power Down Mode CS = VIH (MIN.), CKE VIH(MIN.) No operating current tCK = min., CS = VIH (MIN.), active state (max. 4 banks) Burst Operating Current tCK = min Read command cycling Auto Refresh Current tCK = min Auto Refresh command cycling Self Refresh Current Self Refresh Mode CKE = 0.2 V Test Condition Symbol -7.5 - -8 max. 140 Unit Note mA
1)
ICC1
150
tCK = min tCK = infinity tCK = min tCK = infinity
CKE VIH(MIN.) CKE VIL(MAX.) -
ICC2P ICC2PS ICC2N ICC2NS ICC3N ICC3P ICC4
2 1 40 5 50 10 150
2 1 35 5 45 10 140
mA mA mA mA mA mA mA
1) 1)
1) 1)
1) 1)
1, 2)
-
ICC5
180
170
mA
1)
ICC6
1.5
1.5
mA
1)
Data Book
6
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HYS 64V8301GU SDRAM-Modules
AC Characteristics 3,4 TA = 0 to 70 C; VSS = 0 V; VDD = 3.3 V 0.3 V, tT = 1 ns Parameter Symbol Limit Values -7.5 PC133-333 min. Clock and Access Time Clock Cycle Time CAS Latency = 3 CAS Latency = 2 System Frequency CAS Latency = 3 CAS Latency = 2 Access Time from Clock CAS Latency = 3 CAS Latency = 2 Clock High Pulse Width Clock Low Pulse Width Setup and Hold Parameters Input Setup Time Input Hold Time Power Down mode Entry Time Power Down Mode Exit Setup Time Mode Register Setup Time Transition Time Common Parameters RAS to CAS Delay Precharge Time Active Command Period Cycle Time Bank to Bank Delay Time CAS to CAS Delay Time (same bank) max. -8 PC100-222 min. max. Unit Note
tCK
7.5 10 - - 133 100 5.4 6 - - 10 10 - - - - 3 3 - - 100 100 6 6 - - ns ns
-
fCK
- - MHz MHz ns ns ns ns
-
tAC
- -
4), 5)
tCH tCL
2.5 2.5
6) 6)
tCS tCH tSB tPDE tESC tT
1.5 0.8 - 1 2 1
- - 1 - - -
2 1 - 1 2 1
- - 1 - - -
ns ns CLK CLK CLK ns
7) 7) 8) 9)
-
tRCD tRP tRAS tRC tRRD tCCD
20 20 45 67.5 15 1
- - 100k - - -
20 20 50 70 16 1
- - 100k - - -
ns ns ns ns ns CLK
- - - - - -
Data Book
7
12.99
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HYS 64V8301GU SDRAM-Modules
AC Characteristics (cont'd)3,4 TA = 0 to 70 C; VSS = 0 V; VDD = 3.3 V 0.3 V, tT = 1 ns Parameter Symbol Limit Values -7.5 PC133-333 min. max. -8 PC100-222 min. max. Unit Note
Refresh Cycle Refresh Period (4096 cycles) Self Refresh Exit Time Read Cycle Data Out Hold Time Data Out to Low Impedance Time Data Out to High Impedance Time DQM Data Out Disable Latency Write Cycle Data Input to Precharge (write recovery) DQM Write Mask Latency Notes 1. These parameters depend on the cycle rate. These values are measured at 133 MHz for -7.5 and at 100 MHz for -8 modules. Input signals are changed once during tCK, excepts for ICC6 and for stand-by currents when tCK = infinity. All values are shown per memory component. 2. These parameters are measured with continuous data stream during read access and all DQ toggling. CL = 3 and BL = 4 are assumed and the VDDQ current is excluded. 3. All AC characteristics are shown for device level. An initial pause of 100 s is required after power-up. Then a Precharge All Banks command must be given followed by eight Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. 4. AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit shown in Figure below. Specified tAC and tOH parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1V/ ns edge rate between 0.8 V and 2.0 V. 5. If clock rising time is longer than 1 ns, a time (tT/2 - 0.5) ns must be added to this parameter. 6. Rated at 1.4 V. 7. If tT is longer than 1 ns, a time (tT - 1) ns must be added to this parameter.
tREF tSREX
- 1
64 -
- 1
64 -
ms CLK
8) 10)
tOH tLZ tHZ tDQZ
3 0 3 -
- - 7 2
3 0 3 -
- - 8 2
ns ns ns CLK
4)
-
11)
-
tWR tDQW
2 0
- -
2 0
- -
CLK CLK
- -
Data Book
8
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HYS 64V8301GU SDRAM-Modules
8. Whenever the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to "wake-up" the device. 9. Timing is a asynchronous. If setup time is not met by rising edge of the clock then the CKE signal is assumed latched on the next cycle. 10.Self Refresh Exit is a synchronous operation and begins on the second positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied after the Self Refresh Exit command is registered. 11.This is referenced to the time at which the output achieved the open circuit condition, not to output voltage levels.
t CH
CLOCK 2.4 V 0.4 V
t CL t SETUP
INPUT
tT
t HOLD
1.4 V
t AC t LZ
OUTPUT
t AC t OH
1.4 V
I/O 50 pF
t HZ
SPT03404
Measurement conditions for tAC and tOH
A serial presence detect storage device - E2PROM - is assembled onto the module. Information about the module configuration, speed, etc. is written into the E2PROM device during module production using a serial presence detect protocol (I2C synchronous 2-wire bus).
Data Book
9
12.99
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HYS 64V8301GU SDRAM-Modules
SPD-Table Byte# Description SPD Entry Value Hex 8M x 64 8M x 64 -7.5 -8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Number of SPD bytes Total Bytes in Serial PD Memory Type Number of Row Addresses (without BS bits) Number of Column Addresses (for 16 SDRAM) Number of DIMM Banks Module Data Width Module Data Width (cont'd) Module Interface Levels SDRAM Cycle Time at CL = 3 SDRAM Access Time from Clock at CL = 3 DIMM Config (Error Det/Corr.) Refresh Rate/Type SDRAM Width, Primary Error Checking SDRAM Data Width Minimum Clock Delay for Back-to-Back Random Column Address Burst Length Supported Number of SDRAM Banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM Module Attributes SDRAM Device Attributes: General 128 256 SDRAM 12 9 1 64 0 LVTTL 7.5/10.0 ns 5.4/6.0 ns none Self-Refresh, 15.6 s x16 n/a 80 08 04 0C 09 01 40 00 01 75 54 00 80 10 00 01 0F 04 06 01 01 0E 80 08 04 0C 09 01 40 00 01 A0 60 00 80 10 00 01 0F 04 06 01 01 00 0E
tCCD = 1 CLK
1, 2, 4, & 8 4 CL = 2 & 3 CS latency = 0 WL = 0
non buffered/non reg. 00
VDD tol. 10%
Data Book
10
12.99
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HYS 64V8301GU SDRAM-Modules
SPD-Table (cont'd) Byte# Description SPD Entry Value Hex 4M x 64 4M x 64 -7.5 -8 23 24 25 26 27 28 29 30 31 32 33 34 35 36-61 62 63 Minimum Clock Cycle Time at CAS Latency = 2 Maximum Data Access Time from Clock for CL = 2 Minimum Clock Cycle Time at CL = 1 Maximum Data Access Time from Clock at CL = 1 Minimum Row Precharge Time Minimum Row Active to Row Active Delay 10.0 ns 6.0 ns not supported not supported 20 ns 15/16 ns 20 ns 45 ns 64 MByte 1.5/2 ns 0.8/1 ns 1.5/2 ns 0.8/1 ns Revision 1.2 - - A0 60 FF FF 14 0F 14 2D 10 15 08 15 08 FF 12 TBD - 64 - - AF FF A0 60 FF FF 14 10 14 2D 10 20 10 20 10 FF 12 TBD XX 64 AF FF
tRRD
Minimum RAS to CAS Delay tRCD Minimum RAS Pulse Width tRAS Module Bank Density (per bank) SDRAM Input Setup Time SDRAM Input Hold Time SDRAM Data Input Setup Time SDRAM Data Input Hold Time SPD Revision Checksum for bytes 0 - 62
Superset Information (may be used in future) -
64-125 Manufacturers Information (optional) (FFH if not used) 126 127 128+ Max. Frequency Specification Details Unused Storage Locations
Data Book
11
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HYS 64V8301GU SDRAM-Modules
Package Outlines L-DIM-168-32 SDRAM DIMM Module Package
133.35 127.35
4 0.1
4 max.
29.31 3
1 3
10 1.27
11 6.35 42.18
40
41 6.35
84
1.27 0.1
91 x 1.27 = 115.57 66.68 2 95
3.125
85
94
124
125
168
17.78
3 min. Detail of Contacts
0.2 0.15 2.54 min.
1 0.05 1.27
GLD09263
Data Book
12
12.99
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